In modern integrated circuits, such as circuits for mixed-mode or radio-frequency applications, a pair of capacitors with equal capacitances is commonly used. The mismatched performance of the capacitor pair determines the accuracy of the resulting digital signal, and thus capacitor pairs with highly matched capacitances are preferred.
FIG. 1 illustrates a conventional capacitor pair, which includes a first capacitor C1 and a second capacitor C2. Capacitors C1 and C2 are identically designed. Each of the capacitors C1 and C2 include a first plurality of fingers and a second plurality of fingers alternately placed. The capacitances of capacitors C1 and C2 are partially determined by the length and number of fingers. Greater capacitors C1 and C2 can be designed by increasing the number of fingers and/or by increasing the length of the fingers.
The capacitor pair illustrated in FIG. 1 has drawbacks, however. Although capacitors C1 and C2 are designed to be identical, the formation processes are sensitive to local environments. For example, one of the capacitors C1 and C2 may be located close to a pattern-sparse region, and the other capacitor may be located close to a pattern-dense region. The different pattern densities cause pattern-loading effects, hence variations in dimensions. As a result, capacitors C1 and C2 mismatch from each other. Typically, process variations increase with the increase in capacitances of capacitors C1 and C2.
To solve the process sensitivity problem, a modified capacitor pair is provided, as is illustrated in FIG. 2. The modified capacitor pair includes four unit capacitors arranged as a two-by-two array, with two of the unit capacitors interconnected to form one capacitor. Each unit capacitor is cross-coupled to another unit capacitor. Such a layout helps reduce process sensitivity.
With the scaling of integrated circuits, new integrated circuit formation methods are used. Particularly, damascene processes are widely used in 0.18 μm technology and below, and thus are also used for the formation of capacitor pairs. Damascene processes typically involve forming dielectric layers; forming openings in the dielectric layers; filling the openings with copper or copper alloys; and planarizing the surface of the dielectric layer and copper using a chemical mechanical polish (CMP) process. Using a CMP process worsens the mismatch performance of capacitor pairs if the capacitor pairs have high capacitances. Accordingly, a new capacitor structure having high mismatch performance and methods for forming the same are needed.